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general description the max8893a/max8893b/max8893c power-manage - ment integrated circuits (pmics) are designed for a variety of portable devices including cellular handsets. the pmics include a high-efficiency step-down dc-dc converter, five low-dropout linear regulators (ldos) with programmable output voltages, individual power-on/ off control inputs, a load switch, and a usb high-speed switch. these devices maintain high efficiency with a low no-load supply current, and the small 3.0mm x 2.5mm wlp package makes them ideal for portable devices. the step-down dc-dc converter utilizes a proprietary 4mhz hysteretic pwm control scheme that allows for ultra-small external components. internal synchronous rectification improves efficiency and eliminates the exter - nal schottky diode that is required in conventional step- down converters. its output voltage is programmable by the i 2 c serial interface and output current is guaranteed up to 500ma. ldo1, ldo4, and ldo5 offer low 45 f v rms output noise and low dropout of only 100mv at 100ma. they deliver up to 300ma, 150ma, and 200ma continuous output cur - rents, respectively. ldo2 and ldo3 each deliver 300ma continuous output current with very low ground current. all ldo output voltages are programmable by the i 2 c serial interface. three standard versions of the pmic are available with different ldo default startup voltages (see table 1). the max8893a/max8893b/max8893c are available in a 3.0mm x 2.5mm, 30-bump wlp package. applications cellular handsets smartphones and pdas features s high-efficiency step-down converter guaranteed 500ma output current up to 4mhz switching frequency programmable output voltage from 0.8v to 2.4v dynamic voltage scaling with programmable ramp rate s three low-noise ldos with programmable output voltages s two low supply current ldos with programmable output voltages s low on-resistance load switch s usb high-speed switch with 15kv esd s individual enable control for all regulators and switches s i 2 c serial interface s overcurrent and thermal protection for all ldos s 3.0mm x 2.5mm x 0. 64 mm, 30 -bump wlp 19-4971; rev 1; 2/10 + denotes a lead(pb)-free/rohs-compliant package. typical operating circuit appears at end of data sheet. ordering information visit www.maximintegrated.com/products/patents for product patent marking information. part temp range pin-package max8893a ewv+ -40 n c to +85 n c 30-bump wlp (3.0mm x 2.5mm) max8893b ewv+ -40 n c to +85 n c 30-bump wlp (3.0mm x 2.5mm) max8893c ewv+ -40 n c to +85 n c 30-bump wlp (3.0mm x 2.5mm) pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in1, in2, batt, com1, com2 to agnd ............. -0.3v to +6.0v buck, ls, enls, enbuck, enldo1, enldo2, enldo3, enldo45, refbp, ldo2, ldo3, scl, sda, enusb, cb, nc1, nc2, no1, no2 to agnd .......................... -0.3v to (v batt + 0.3v) ldo1, ldo4, ldo5 to agnd .................. -0.3v to (v in2 + 0.3v) pgnd to agnd .................................................... -0.3v to +0.3v lx current ..................................................................... 1.5a rms lx to agnd (note 1) ................................ -0.3v to (v in1 + 0.3v) continuous power dissipation (t a = +70 n c) 30-bump, 3.0mm x 2.5mm wlp (derate 20.0mw/ n c above +70 n c) ............................................................. 1600mw junction-to-ambient thermal resistance ( ja ) (note 2) ........................................................................ 50 n c/w operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c bump temperature (soldering) infrared (15s) ............................................................... +200 n c vapor phase (20s) ....................................................... +215 n c electrical characteristics ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) absolute maximum ratings note 1: lx has internal clap diodes to pgnd and in1. applications that forward bias these diodes should take care not to exceed the ics package-dissipation limits. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-lay - er board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . parameter conditions min typ max unit input supply range 2. 7 5.5 v shutdown supply current v cb = 0v or v in , v enusb = v in , v enls = v enbuck = v enldo1 = v enldo2 = v enldo3 = v enldo45 = 0v 0.6 5 f a no-load supply current no load on buck , ldo1, ldo2 , ldo3, ldo4, and ldo5 , v enusb = 0v, v enls = v in 160 200 f a light-load supply current buck on with 500 f a load , all ldos on with no load, v enusb = 0v, v enls = v in 315 f a undervoltage lockout undervoltage lockout (note 5) v in_ rising 2.70 2.85 3.05 v v in_ falling 2.35 2.55 thermal shutdown thermal shutdown threshold t a rising 160 n c thermal shutdown hysteresis 10 n c reference reference bypass output voltage 0.786 0.8 00 0.814 v ref supply rejection 2. 7 v p v in p 5.5v 0.2 mv/v logic and control inputs input low level enls, enbuck, enldo1, enldo2, enldo3, enldo45, enusb , sda, scl , 2. 7 v p v in p 5.5v 0.4 v input high level enls, enbuck, enldo1, enldo2, enldo3, enldo45, enusb , sda, scl , 2. 7 v p v in p 5.5v 1.4 v maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
3 electrical characteristics (continued) ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) parameter conditions min typ max unit logic input current sda, scl , 0v < v in < 5.5v t a = + 25 n c -1 +1 f a t a = + 85 n c 0.1 enusb pul lu p r esistor to batt 400 800 1600 k i enls, enbuck, enldo1, enldo2, enldo3, enldo45, pulldown resistor to agnd 400 800 1600 k i step-down dc-dc converter (buck) supply current i load = 0a, no switching 25 f a programmable output voltage i load = 100 ma, p rogrammable output voltage 0.8v to 2.4v in 100mv steps 0.776 0.800 0.824 v 0.90 0.97 1.00 1.03 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.231 2.300 2.369 2.328 2.400 2.472 output-voltage line regulation v in = 2. 7 v to 5.5v 0.3 %/v lx l eakage c urrent v lx = 0 v or 5.5v t a = + 25 n c -1 + 1 f a t a = + 85 n c 0.1 current limit p-mosfet switch 600 990 1500 ma n-mosfet rectifier 40 0 7 00 1300 on-resistance p-mosfet switch, i lx = -40ma 0.65 i n-mosfet rectifier, i lx = 40ma 0.4 rectifier off current threshold i lxoff 30 ma minimum on- and off-times t on , t off 70 ns shutdown output resistance buck_aden = 1, v enbuck = 0v 300 i maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
4 electrical characteristics (continued) ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) parameter conditions min typ max unit ldo1 input voltage range 2.7 5.5 v programmable output voltage i load = 25ma , p rogrammable output voltage 1.6v to 3.3v in 100mv steps 1.552 1.6 00 1.648 v 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 2.910 3.000 3.090 3.1 3.2 3.201 3.300 3.399 output voltage accuracy v in = 5.5v with i load = 1ma, and v in = 3.2v with i load = 300ma (max8893a) 2.716 2.800 2.884 v v in = 5.5v with i load = 1ma, and v in = 3.0v with i load = 300ma (max8893b) 2.522 2.600 2.678 v in = 5.5v with i load = 1ma, and v in = 2.7v with i load = 300ma (max8893c) 1.746 1.800 1.854 output current 300 ma current limit v ldo1 = 0v 550 ma dropout voltage i load = 200ma, t a = + 2 5 n c 200 mv load regulation 1ma < i load < 300ma v enldo1 = v batt 25 mv power-supply rejection d v ldo1 / d v in2 10hz to 10khz, c ldo1 = 1 f f, i load = 30ma 75 db output noise voltage 100hz to 100khz, c ldo1 = 1 f f, i load = 30ma 45 f v rms output capacitor for stable operation (note 6) 0ma < i load < 300ma 1.4 2.2 f f 0ma < i load < 150ma 0.7 1.0 ground current i load = 500 f a 21 f a startup t ime from s hutdown c ldo1 = 2.2 f f , i load = 3 0 0ma 40 f s shutdown output resistance ldo1_ad en = 1 , v enldo1 = 0v 300 i maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
5 electrical characteristics (continued) ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) parameter conditions min typ max unit ldo2 input voltage range 2.7 5.5 v programmable output voltage i load = 25ma , p rogrammable output voltage 1.2v to 3.3v in 100mv steps 1.164 1.2 00 1.236 v 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.134 2.200 2.266 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.201 3.300 3.399 output voltage accuracy v in = 5.5v with i load = 1ma, and v in = 3.0v with i load = 300ma 2.522 2.600 2.678 v output current 300 ma current limit v ldo 2 = 0v 550 ma dropout voltage i load = 200ma, t a = + 2 5 n c 200 mv load regulation 1ma < i load < 300ma v enldo2 = v batt 25 mv power-supply rejection d v ldo 2 / d v batt 10hz to 10khz, c ldo 2 = 1 f f, i load = 30ma 60 db output noise voltage 100hz to 100khz, c ldo 2 = 1 f f, i load = 30ma 80 f v rms output capacitor for stable operation (note 6) 0ma < i load < 300ma 1.4 2.2 f f 0ma < i load < 150ma 0.7 1.0 ground current i load = 500 f a 21 f a startup t ime from s hutdown c ldo 2 = 1 f f, i load = 3 0 0ma 40 f s shutdown output resistance ldo2_a den = 1 , v enldo2 = 0v 300 i maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
6 electrical characteristics (continued) ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) parameter conditions min typ max unit ldo3 input voltage range 2.7 5.5 v programmable output voltage i load = 25ma , p rogrammable output voltage 1.6v to 3.3v in 100mv steps 1.552 1.6 00 1.648 v 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 2.910 3.000 3.090 3.10 3.20 3.201 3.300 3.399 output voltage accuracy v in = 5.5v with i load = 1ma, and v in = 3.7v with i load = 300ma 3.201 3.300 3.399 v output current 300 ma current limit v ldo 3 = 0v 550 ma dropout voltage i load = 200ma, t a = + 2 5 n c 200 mv load regulation 1ma < i load < 300ma v enldo3 = v batt 25 mv power-supply rejection d v ldo 3 / d v batt 10hz to 10khz, c ldo 3 = 1 f f, i load = 30ma 60 db output noise voltage 100hz to 100khz, c ldo 3 = 1 f f, i load = 30ma 80 f v rms output capacitor for stable operation (note 6) 0ma < i load < 300ma 1.4 2.2 f f 0ma < i load < 150ma 0.7 1.0 ground current i load = 500 f a 21 f a startup t ime from s hutdown c ldo 3 = 2.2 f f , i load = 3 0 0ma 40 f s shutdown output resistance ldo3_ad en = 1 , v enldo3 = 0v 300 i maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
7 electrical characteristics (continued) ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) ldo 4 input voltage range 2.7 5.5 v programmable output voltage i load = 25ma , p rogrammable output voltage 0.8v to 3.3v in 100mv steps 0.776 0.800 0.824 v 0.90 1.00 1.10 1.20 1.30 1.358 1. 400 1.442 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.201 3.300 3.399 output voltage accuracy v in = 5.5v with i load =1ma, and v in = 3.4v with i load = 150ma (max8893a) 2.910 3.000 3.090 v v in = 5.5v with i load = 1ma, and v in = 3.7v with i load = 150ma (max8893b/max8893c) 3.201 3.300 3.399 output current 150 ma current limit v ldo 4 = 0v 360 ma dropout voltage i load = 1 00ma 100 mv load regulation 1ma < i load < 15 0ma, v enldo4 = v batt 25 mv power-supply rejection d v ldo 4 / d v in2 10hz to 10khz, c ldo 4 = 1 f f, i load = 30ma 75 db output noise voltage 100hz to 100khz, c ldo 4 = 1 f f, i load = 30ma 45 f v rms output capacitor for stable operation 0ma < i load < 150ma (note 6 ) 0.7 1.0 f f maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
8 electrical characteristics (continued) ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) parameter conditions min typ max unit ground current i load = 500 f a 21 f a startup time from shutdown c ldo4 = 1.0 f f , i load = 150ma 40 f s shutdown output resistance ldo4_aden = 1, v enldo4 = 0v 300 i ldo5 input voltage range 2. 7 5.5 v programmable output voltage i load = 100ma, p rogrammable output voltage 0.8v to 3.3v in 100mv steps 0.776 0.800 0.824 v 0.90 1.00 1.10 1.20 1.30 1.358 1. 400 1.442 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.201 3.300 3.399 output voltage accuracy v in = 5.5v with i load = 1ma, and v in = 3.4v with i load = 150ma (max8893a) 0.970 1.000 1.030 v v in = 5.5v with i load = 1ma, and v in = 3.4v with i load = 150ma (max8893b) 2.716 2.800 2.884 v in = 5.5v with i load = 1ma, and v in = 3.4v with i load = 150ma (max8893c) 2.910 3.000 3.090 output current 200 ma current limit v ldo5 = 0v 460 ma dropout voltage i load = 100ma 100 mv maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
9 electrical characteristics (continued) ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) parameter conditions min typ max unit load regulation 1ma < i load < 150ma v enldo5 = v batt 25 mv power-supply rejection d v ldo5 / d v in2 10hz to 10khz, c ldo5 = 1 f f, i load = 30ma 75 db output noise voltage 100hz to 100khz, c ldo5 = 1 f f, i load = 30ma 45 f v rms output capacitor for stable operation (note 6) 0ma < i load < 2 00ma 1.4 2.2 f f 0ma < i load < 150ma 0.7 1.0 ground current i load = 500 f a 21 f a startup time from shutdown c ldo5 = 2.2 f f , i load = 200ma 40 f s shutdown output resistance ldo5_aden = 1, v enldo5 = 0v 300 i usb high-speed switch operating power-supply range 2.7 5.5 v supply current v enusb = 0v, v cb = 0v or v batt v batt = 3.0v 0.6 f a v batt = 5.5v 3 fault protection trip threshold (v fp ) com _ only, t a = +25 n c v in + 0.6 v in + 0.8 v in + 1.0 v on-resistance (r on ) v com_ = 0v to v batt 5 10 i v com_ = 3.6v, v batt = 3.0v 5.5 on-resistance match between channels ( d r on ) v batt = 3.0v, v com_ = 2v (note 7) 0.1 1 i on-resistance flatness (r flat ) v batt = 3.0v, v com_ = 0v to v in (note 8) 0.1 i off-leakage current (i com_(off) ) v batt = 4.5v, v com_ = 0v or 4.5v, v no_ , v nc_ = 4.5v or 0v -250 +250 na v batt = 5.5v, v com_ = 0v or 5.5v, v no_ , v nc_ with 50 f a sink current to agnd 180 f a on-leakage current (i com_(on) ) v batt = 5.5v, v com_ = 0v or 5.5v, v no_ , and v nc_ are unconnected -250 +250 na usb high-speed switch ac performance on-channel -3db bandwidth (bw) r l = r s = 50 i , signal = 0dbm 950 mhz off-isolation (v iso ) v no_ , v nc_ = 0dbm, r l = r s = 50 i , figure 1 f = 10mhz -48 db f = 250mhz -20 f = 500mhz -17 crosstalk (v ct ) v no_ , v nc_ = 0dbm, r l = r s = 50 i , figure 1 (note 9) f = 10mhz -73 db f = 250mhz -54 f = 500mhz -33 usb high-speed switch logic input (cb) input logic-high (v ih ) 1.4 v input logic-low (v il ) 0. 4 v input leakage current (i in ) -250 +250 na maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
10 electrical characteristics (continued) ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) parameter conditions min typ max unit usb high-speed switch dynamic turn-on time (t on ) v no_ or v nc_ = 1.5v, r l = 300 i , c l = 35pf, v /enusb = v batt to 0v, figure 2 1 5 f s turn-off time (t off ) v no_ or v nc_ = 1.5v, r l = 300 i , c l = 35pf, v /enusb = 0v to v batt , figure 2 1 5 f s propagation delay (t plh , t phl ) r l = r s = 50 i , figure 3 100 ps fault protection response time (t fp ) v com_ = 0v to 5v step, r l = r s = 50 i , v batt = 3.3v, figure 4 0.5 5.0 f s fault protection recovery time (t fpr ) v com_ = 5v to 0v step, r l = r s = 50 i , v batt = 3.3v, figure 4 100 f s output skew between switches (t sk ) skew between switch 1 and 2, r l = r s = 50 i , figure 3 (note 6) 40 ps no_ or nc_ off-capacitance (c no(off) or c nc(off) ) f = 1mhz, figure 5 (note 6) 2 pf com off-capacitance (c com(off) ) (note 6) f = 1mhz, figure 5 5.5 pf f = 240 mhz, figure 5 4.8 com on-capacitance (c com(on) ) (note 6) f = 1mhz, figure 5 6.5 pf f = 240 mhz, figure 5 5.5 total harmonic distortion plus noise v com_ = 1v p-p , v bias = 1v, r l = r s = 50 i , f = 20hz to 20khz 0.03 % usb high-speed switchesd protection enusb , cb, nc1, nc2, no1, no2 human body model 2 kv com1, com2 human body model 15 kv iec 61000-4-2 air-gap discharge 15 iec 61000-4-2 contact discharge 8 i 2 c serial interface (figure 8) clock frequency 400 khz bus-free time between start and stop (t buf ) 1.3 f s hold time repeated start condition (t hd_sta ) 0.6 f s scl low period (t low ) 1.3 f s scl high period (t high ) 0.6 f s setup time repeated start condition (t su_sta ) 0.6 f s sda hold time (t hd_dat ) 0 f s sda setup time (t su_dat ) 100 ns setup time for stop condition (t su_sto ) 0.6 f s maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
11 electrical characteristics (continued) ( typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (notes 3, 4) note 3: v in1 , v in2 , and v batt are connected together and single input is referred to as v in . note 4: all units are 100% production tested at t a = +25 n c. limits over the operating temperature range are guaranteed by design. note 5: when the input voltage is greater than 2.85v (typ), the uvlo comparator trips, and the threshold is reduced to 2.35v (typ). this allows the system to start normally even if the input voltage decays to 2.35v. note 6: not production tested; guaranteed by design. note 7: d r on(max) = |r on(ch1) - r on(ch2) |. note 8: flatness is defined as the difference between the maximum and minimum value of on-resistance, as measured over specified analog signal ranges. note 9: between any two switches. parameter conditions min typ max unit maximum pulse width of spikes suppressed 50 ns load switch (ls) input supply o perating range (v buck ) after v buck starts up 0.8 2.4 v on-resistance (r ds(on) ) v buck = 1.0v, i ls = 300ma , t a = + 25 n c 50 100 m i turn -o n d elay t ime (t on_dly ) v ls = 2.4v, r l = 400 i , v enls = 1.8v , register lstod = 0 (note 6 ) c l = 0.1 f f 0.85 f s c l = 1 f f 0.85 c l = 3 f f 0.85 v ls = 2.4v, r l = 400 i , v enls = 1.8v , register lstod = 1 c l = 0.1 f f 30 c l = 1 f f 34 c l = 3 f f 37 ls r ise t ime ( t r ) v ls = 2.4v, r l = 400 i , v enls = 1.8v, register ls rt = 0 c l = 0.1 f f 10 f s c l = 1 f f (note 6 ) 10 c l = 3 f f (note 6 ) 10 v ls = 2.4v, r l = 400 i , v enls = 1.8v , register ls r t = 1 c l = 0.1 f f 25 c l = 1 f f 27 c l = 3 f f 30 v ls = 2.4v, r l = 400 i , v enls = 1.8v , register ls r t = 2 c l = 0.1 f f 100 c l = 1 f f 100 c l = 3 f f 100 v ls = 2.4v, r l = 400 i , v enls = 1.8v , register lsrt = 3 c l = 0.1 f f 300 c l = 1 f f 300 c l = 3 f f 300 turn -o ff d elay t ime ( t off_dly ) v ls = 2.4v, r l = 400 i , v enls = 1.8v c l = 0.1 f f 11 f s c l = 1 f f 11 c l = 3 f f 11 ls f all t ime ( t f ) v ls = 2.4v, r l = 400 i , v enls = 1.8v c l = 0.1 f f 15 f s c l = 1 f f 150 c l = 3 f f 447 shutdown output resistance v ls = 2.4v, v enls = 0v, l s _ad en = 1 100 200 i maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
12 typical operating characteristics (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) usb switch on-resistance vs. com voltage max8893a toc03 com voltage (v) on-resistance (i) 5 4 3 2 1 3.0 3.5 4.0 4.5 5.0 5.5 2.5 06 ta = +25c v batt = 3.0v v batt = 3.7v v batt = 4.2v fault protection com leakage current vs. temperature max8893a toc05 temperature (c) com leakage current (na) 60 35 10 -15 37 39 41 43 45 35 -40 85 no-load supply current vs. temperature max8893a toc02 temperature (c) supply current ( a) 60 35 10 -15 110 120 130 140 150 160 170 180 190 200 100 -40 85 v batt = 3.0v v batt = 3.7v v batt = 4.2v no-load supply current vs. supply voltage max8893a toc01 supply voltage (v) supply current ( a) 5.0 4.5 4.0 3.5 3.0 50 100 150 200 250 0 2.5 5.5 step-down and all ldos enusb = gnd, enls = batt step-down and all ldos enusb = batt, enls = gnd step-down only usb switch on-resistance vs. com voltage max8893a toc04 com voltage (v) on-resistance (i) 4 3 2 1 3.0 3.5 4.0 4.5 5.0 5.5 2.5 05 v batt = 3.7v t a = +85c t a = +60c t a = +35c t a = +10c t a = -15c t a = -40c logic threshold voltage vs. supply voltage max8893a toc06 supply voltage (v) threshold voltage (v) 5.0 4.5 4.0 3.5 3.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 2.5 5.5 falling rising maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
13 typical operating characteristics (continued) (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) load switch on-resistance vs. temperature max8893a toc07 temperature (c) on-resistance (mi) 60 35 10 -15 50 60 70 80 90 40 -40 85 v buck = 1.0v, i ls = 500ma load switch turn-on/off waveform max8893a toc09 2v/div 500mv/div 200ma/div v ls v enls i ls 20s/div 10i load, c ls = 1.0 f load switch voltage drop vs. load current max8893a toc11 load current (ma) v buck - v ls (mv) 400 300 200 100 10 20 30 40 0 0 500 v buck = 1.0v load switch on-resistance vs. battery voltage max8893a toc08 battery voltage (v) on-resistance (mi) 5.0 4.5 4.0 3.5 3.0 50 60 70 80 90 40 2.5 5.5 v buck = 1.0v load switch turn-on/off waveform max8893a toc10 2v/div 500mv/div 500ma/div v ls v enls i ls 20s/div 2i load c ls = 1.0 f step-down efficiency vs. load current max8893a toc12 load current (ma) efficiency (%) 100 10 1.0 10 20 30 40 50 60 70 80 90 100 0 0.1 1000 v batt = 3.0v v batt = 3.7v v batt = 4.2v v buck = 1.0v maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
14 typical operating characteristics (continued) (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) step-down switching frequency vs. load current max8893a toc13 load current (ma) switching frequency (khz) 400 300 200 100 400 800 1200 1600 2000 2400 2800 3200 3600 4000 0 0 500 v batt = 3.7v v buck = 1.0v step-down light-load switching waveforms max8893a toc15 50mv/div (ac-coupled) 2v/div 100ma/div v lx v buck i l 10s/div 1ma load, v buck = 1.0v step-down heavy-load switching waveforms max8893a toc17 v lx v buck i l 400ns/div 300ma load, v buck = 1.0v 20mv/div (ac-coupled) 2v/div 200ma/div step-down output voltage vs. load current max8893a toc14 load current (ma) output voltage (v) 400 300 200 100 0.98 0.99 1.00 1.01 1.02 0.97 0 500 v batt = 4.2v v batt = 3.0v v buck = 1.0v v batt = 3.7v step-down medium-load switching waveforms max8893a toc16 20mv/div (ac-coupled) 2v/div 100ma/div v lx v buck i l 400ns/div 40ma load, v buck = 1.0v step-down startup and shutdown waveform max8893a toc18 2v/div 500mv/div 500ma load, v buck = 1.0v 100ma/div v enbuck v buck i in 100s/div maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
15 typical operating characteristics (continued) (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) step-down line transient waveform max8893a toc19 500mv/div 20ma/div (ac-coupled) v buck v batt 10s/div 10i load 4v 3.5v ldo1 dropout voltage vs. load current max8893a toc21 load current (ma) dropout voltage (mv) 250 200 150 100 50 50 100 150 200 0 0 300 ldo1 output voltage vs. input voltage max8893a toc23 input voltage (v) output voltage (v) 5.1 4.7 4.3 3.9 3.5 3.1 2.55 2.60 2.65 2.70 2.75 2.80 2.50 2.7 5.5 300ma load step-down load transient waveform max8893a toc20 50mv/div 200ma/div i out v buck 20s/div 5ma5 ma 300ma ldo1 output-voltage error vs. load current max8893a toc22 load current (ma) output-voltage error (mv) 250 200 150 100 50 -40 -30 -20 -10 0 -50 0 300 ldo1 line transient waveform max8893a toc24 500mv/div 10mv/div (ac-coupled) v ldo1 v batt 10s/div 4v 3.5v 10i load maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
16 typical operating characteristics (continued) (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) ldo1 load transient waveform max8893a toc25 200ma/div 200mv/div (ac-coupled) i out v ldo1 20s/div 5ma5 ma 300ma ldo2 dropout voltage vs. load current max8893a toc27 load current (ma) dropout voltage (mv) 250 200 150 100 50 50 100 150 200 0 0 300 ldo2 output voltage vs. input voltage max8893a toc29 input voltage (v) output voltage (v) 5.1 4.7 4.3 3.9 3.5 3.1 2.50 2.55 2.60 2.65 2.45 2.7 5.5 300ma load ldo1 startup and shutdown waveform max8893a toc26 2v/div 1v/div 300ma load, v ldo1 = 2.8v 500ma/div v enlod1 v ldo1 i in 100s/div ldo2 output-voltage error vs. load current max8893a toc28 load current (ma) output-voltage error (mv) 250 200 150 100 50 -40 -30 -20 -10 0 -50 0 300 ldo2 line transient waveform max8893a toc30 10mv/div (ac-coupled) 500mv/div v batt 4v 3.5v 10 i load v ldo2 10s/div maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
17 typical operating characteristics (continued) (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) ldo2 load transient waveform max8893a toc31 200mv/div (ac-coupled) 200ma/div i out v ldo1 20s/div 300ma 5ma 5ma ldo3 dropout voltage vs. load current max8893a toc33 load current (ma) dropout voltage (mv) 250 200 150 100 50 50 100 150 200 0 0 300 ldo3 output voltage vs. input voltage max8893a toc35 input voltage (v) output voltage (v) 5.1 4.7 3.1 3.5 3.9 4.3 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 2.5 2.7 5.5 300ma load ldo2 startup and shutdown waveform max8893a toc32 2v/div 1v/div 300ma load, v ldo2 = 2.6v 500ma/div v enldo2 v ldo2 i in 100s/div ldo3 output-voltage error vs. load current max8893a toc34 load current (ma) output-voltage error (mv) 250 200 150 100 50 -40 -30 -20 -10 0 -50 0 300 ldo3 line transient waveform max8893a toc36 10mv/div (ac-coupled) 500mv/div v batt 4v 3.5v 10 i load v ldo3 10s/div maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
18 typical operating characteristics (continued) (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) ldo3 load transient waveform max8893a toc37 200mv/div (ac-coupled) 200ma/div i out 300ma 5ma 5ma v ldo3 20s/div ldo4 dropout voltage vs. load current max8893a toc39 load current (ma) dropout voltage (mv) 120 90 60 30 20 40 60 80 100 0 0 150 ldo3 startup and shutdown waveform max8893a toc38 2v/div 2v/div 300ma load, v ldo3 = 3.3v 500ma/div v enldo3 v ldo3 i in 100s/div ldo4 output-voltage error vs. load current max8893a toc40 load current (ma) output-voltage error (mv) 120 90 60 30 -40 -30 -20 -10 0 -50 0 150 maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
19 typical operating characteristics (continued) (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) ldo4 output voltage input voltage max8893a toc41 input voltage (v) output voltage (v) 5.1 4.7 4.3 3.9 3.5 3.1 2.6 2.7 2.8 2.9 3.0 2.5 2.7 5.5 150ma load ldo4 load transient waveform max8893a toc43 200mv/div (ac-coupled) 200ma/div i out 5ma 5ma 150ma v ldo4 20s/div ldo4 line transient waveform max8893a toc42 10mv/div (ac-coupled) 500mv/div v batt 4v 3.5v 20 i load v ldo4 10s/div ldo5 dropout voltage vs. load current max8893a toc44 load current (ma) dropout voltage (mv) 160 120 80 40 30 60 90 120 150 0 0 200 maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
20 typical operating characteristics (continued) (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) ldo4 output-voltage error vs. load current max8893a toc45 load current (ma) output-voltage error (mv) 160 120 80 40 -40 -30 -20 -10 0 -50 0 200 ldo4 and ldo5 startup and shutdown waveform max8893a toc49 2v/div 2v/div 1v/div 500ma/div v enldo45 v ldo5 v ldo4 i in 100s/div v ldo4 = 3.0v, 150ma load v ldo5 = 1.0v, 200ma load ldo5 line transient waveform max8893a toc47 10mv/div (ac-coupled) 500mv/div v batt 4v 3.5v 5 i load v ldo5 10s/div ldo5 output voltage vs. input voltage max8893a toc46 input voltage (v) output voltage (v) 5.1 4.7 4.3 3.9 3.5 3.1 0.98 0.99 1.00 1.01 1.02 0.97 2.7 5.5 200ma load power-up sequencing (max8893a) max8893a toc50 4v/div 4v/div 5v/div 5v/div 2v/div 2v/div 2v/div v ldo1 v ldo2 v ldo3 v ldo4 v en_ v buck v ldo5 5i load 1.0v 2.8v 2.6v 3.3v 3.0v 1.0v 100s/div ldo5 load transient waveform max8893a toc48 200mv/div (ac-coupled) 200ma/div i out 5ma 5ma 200ma v ldo5 20s/div maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
21 typical operating characteristics (continued) (typical operating circuit , v in = 3.7v, c batt = c in1 = c in2 = 2.2 f f, c refbp = 0.1 f f, t a = +25 n c, unless otherwise noted.) total harmonic distortion plus noise vs. frequency max8893a toc53 frequency (hz) thd+n (%) 10,000 1000 100 0.01 0.1 1 0.001 10 100,000 r l = 600i eye diagram max8893a toc55 0.5 0.4 0.3 0.2 0.1 differential signal (v) 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 0.2 0.4 0.6 0.8 1.0 1.4 1.6 1.8 2.0 1.2 time (x 10 -9 )s power-up sequencing (max8893b) max8893a toc51 4v/div 4v/div 5v/div 5v/div 5v/div 2v/div 2v/div v ldo1 v ldo2 v ldo3 v ldo4 v en_ v buck v ldo5 1.0v 2.6v 2.6v 3.3v 3.3v 2.8v 100s/div frequency response max8893a toc54 frequency (mhz) magnitude (db) 100 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 1 1000 on-loss off-isolation crosstalk power-up sequencing (max8893c) max8893a toc52 4v/div 4v/div 5v/div 5v/div 5v/div 2v/div 2v/div v ldo1 v ldo2 v ldo3 v ldo4 v en_ v buck v ldo5 1.0v 1.8v 2.6v 3.3v 3.3v 3.0v 100s/div maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
22 test circuits/timing diagrams figure 1. usb high-speed switch off-isolation and crosstalk figure 2. usb high-speed switch switching time switch is enabled. measurements are standardized against shorts at ic terminals. off-isolation is measured between com_ and "off" no_ or nc_ terminal on each switch. crosstalk is measured from one channel to the other channel. signal direction through switch is reversed; worst values are recorded. v out cb nc1 com1 no1* v in max8893a max8893b max8893c off-isolation = 20log v out v in crosstalk = 20log v out v in network analyzer 50i 50i 50i 50i meas ref 0v or v cc 50i *for crosstalk this pin is no2. nc2 and com2 are open . t r < 5ns t f < 5ns 50% v il logic input r l com c l includes fixture and stray capacitance. v out = v in_ ( r l ) r l + r on v in_ v ih t off 0v no_ or nc_ 0.9 x v 0ut 0.1 x v out t on v out switch output logic input in depends on switch configuration; input polarity determined by sense of switch. c l v out max8893a max8893b max8893c en (en) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
23 figure 3. usb high-speed switch output signal skew, rise/fall time, propagation delay test circuits/timing diagrams (continued) v in+ v in- cb v out+ v out- v in+ v in- v out+ v out- nc1 or no1 nc2 or no2 com1 com2 0v v cc v cc v cc v cc 0v 0v 0v t plhx t phlx t inrise t outrise t outfall t plh = t plhx or t plhy t phl = t phlx or t phly t sk(o) = |t plhx - t plhy | or |t phlx - t phly | t sk(p) = |t plhx - t phlx | or |t plhy - t phly | 50% 50% 50% 50% 90% 10% 10% 90% 10% 10% r l r l 50% 50% 50% 50% t infall 90% 90% t phly t plhy r s r s v il to v ih max8893a max8893b max8893c maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
24 test circuits/timing diagrams (continued) figure 4. usb high-speed switch fault-protection response/ recovery time figure 5. usb high-speed switch channel off-/on-capacitance pin configuration v fp v cc = 3.3v t fp t fpr 5v 3v 0v 3v 0v v com v no_ v nc_ capacitance meter nc_ or no_ com cb v il or v ih max8893a max8893b max8893c max8893a/max8893b/max8893c ldo2 ldo3 batt ldo1 23 4 1 a cb enusb enldo1 refbp b nc1 nc2 top view (bumps on bottiom) wlp (3.0mm x 2.5mm) enldo2 in1 5 enbuck enls in2 c no1 no2 enldo3 enldo45 ldo5 d com1 com2 agnd ls lx 6 pgnd buck scl sda ldo4 e maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
25 pin description pin name function a1 ldo1 300ma ldo1 output. bypass ldo1 to agnd with a 2.2 f f ceramic capacitor. the output voltage is programmable from 1.6v to 3.3v in 100mv steps. the output impedance of ldo1 is 300 i when disabled with the ldo1_aden bit set to 1. a2 ldo2 300ma ldo2 output. bypass ldo2 to agnd with a 2.2 f f ceramic capacitor. the output voltage is programmable from 1.2v to 3.3v in 100mv steps. the output impedance of ldo2 is 300 i when disabled with the ldo2_aden bit set to 1. a3 ldo3 300ma ldo3 output. bypass ldo3 to agnd with a 2.2 f f ceramic capacitor. the output voltage is programmable from 1.6v to 3.3v in 100mv steps. the output impedance of ldo3 is 300 i when disabled with the ldo3_aden bit set to 1. a4 batt supply voltage to the control section, ldo2, ldo3, and usb switch. connect a 2.2 f f ceramic capacitor from batt to agnd. a5 in1 supply voltage to the step-down converter. connect a 2.2 f f input ceramic capacitor from in1 to pgnd. a6 lx inductor connection for step-down converter. lx is internally connected to the drain of the internal p-channel mosfet and the drain of the internal n-channel synchronous rectifier. the output impedance of lx is 300 i when the step-down converter is disabled with the buck_aden bit set to 1. b1 refbp reference noise bypass. bypass refbp to agnd with a 0.1 f f ceramic capacitor to reduce noise on the ldo outputs. refbp is high impedance in shutdown. b2 cb digital control input for usb high-speed switch. drive cb low to connect com1 to nc1 and com2 to nc2. drive cb high to connect com1 to no1 and com2 to no2. b3 enusb active-low enable input for usb high-speed switch. drive enusb high to put the switch in high impedance. drive enusb low for normal operation. b4 enldo1 enable input for ldo1. drive enldo1 high to turn on the ldo1. drive enldo1 low to turn off the ldo1. ldo1 can also be enabled/disabled through the i 2 c interface. enldo1 and i 2 c control bit are logically ored. enldo1 has an internal 800k i pulldown resistor. b5 enbuck enable input for the step-down converter. drive enbuck high to turn on the step-down converter. drive enbuck low to turn off the step-down converter. the step-down converter can also be enabled/ disabled through the i 2 c interface. enbuck and i 2 c control bit are logically ored. enbuck has an internal 800k i pulldown resistor. b6 pgnd power ground for step-down converter c1 in2 supply voltage to ldo1, ldo4, and ldo5. connect a 2.2 f f input ceramic capacitor from in2 to agnd. maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
26 pin description (continued) pin name function c2 nc1 normally closed terminal for usb switch 1. nc1 is high impedance in shutdown. c3 nc2 normally closed terminal for usb switch 2. nc2 is high impedance in shutdown. c4 enldo2 enable input for ldo2. drive enldo2 high to turn on the ldo2. drive enldo2 low to turn off the ldo2. ldo2 can also be enabled/disabled through the i 2 c interface. enldo2 and i 2 c control bit are logically ored. enldo2 has an internal 800k i pulldown resistor. c5 enls enable input for load switch . drive enls high to turn on the load switch. drive enls low to turn off the load switch. the load switch can also be enabled/disabled through the i 2 c interface. enls and i 2 c control bit are logically ored. enls has an internal 800k i pulldown resistor. c6 buck voltage feedback for step-down converter d1 ldo5 200ma ldo5 output. bypass ldo5 to agnd with a 2.2 f f ceramic capacitor. the output voltage of ldo5 is programmable from 0.8v to 3.3v in 100mv steps. the output impedance of ldo5 is 300 i when disabled with the ldo5_aden bit set to 1. d2 no1 normally open terminal for usb switch 1. no1 is high impedance in shutdown. d3 no2 normally open terminal for usb switch 2. no2 is high impedance in shutdown. d4 enldo3 enable input for ldo3. drive enldo3 high to turn on the ldo3. drive enldo3 low to turn off the ldo3. ldo3 can also be enabled/disabled through the i 2 c interface. enldo3 and i 2 c control bit are logically ored. enldo3 has an internal 800k i pulldown resistor. d5 enldo45 enable input for ldo4 and ldo5. drive enldo45 high to turn on the ldo4 and ldo5. drive enldo45 low to turn off the ldo4 and ldo5. ldo4 and ldo5 can also be enabled/disabled individually through the i 2 c interface. enldo45 and i 2 c control bits (eldo4 and eldo5) are logically ored. enldo45 has an internal 800k i pulldown resistor. d6 scl i 2 c-compatible serial interface clock high-impedance input e1 ldo4 150ma ldo4 output. bypass ldo4 to gnd with a 1 f f ceramic capacitor. the output voltage of ldo4 is programmable from 0.8v to 3.3v in 100mv steps. the output impedance of ldo4 is 300 i when disabled with the ldo4_aden bit set to 1. e2 com1 common terminal for usb high switch 1 e3 com2 common terminal for usb high switch 2 e4 agnd analog ground. ground for all the ldos, control section, and usb switches. e5 ls load switch output. ls is connected to the drain of an internal p-channel mosfet. v ls = v buck - r ds(on) (p-channel mosfet) x load current. e6 sda i 2 c-compatible serial interface data high-impedance input maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
27 figure 6. block diagram and application circuit c in2 2.2f c batt 2.2f c ls 1f c buck 2.2f c ldo1 2.2f c ldo2 2.2f c ldo3 2.2f c ldo4 1.0f c ldo5 2.2f v buck , 0.8v to 2.4v 100mv step, 500ma v ldo1 , 1.6v to 3.3v 100mv step, 300ma v ldo2 , 1.2v to 3.3v 100mv step, 300ma enbuck enldo1 v ldo3 , 1.6v to 3.3v 100mv step, 300ma enldo2 v ldo4 , 0.8v to 3.3v 100mv step, 150ma enldo3 v ldo5 , 0.8v to 3.3v 100mv step, 200ma enldo45 2.2h in1 batt in2 c in1 2.2f li+ battery ls enls buck lx pgnd enbuck ldo1 enldo1 ldo2 enldo2 ldo3 enldo3 ldo4 enldo45 ldo5 nc1 en in usb high s/w nc2 no1 no2 enusb cb com1 com2 load switch control en en en pgnd lx vbuck in in out en out en out en out en out in in in in step-down converter ldo1 analog ldo ldo2 ldo3 ldo4 analog ldo ldo5 analog ldo enusb c refbp 0.1f refbp scl scl sda sda i 2 c and logic agnd usbsel max8893a max8893b max8893c maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
28 detailed description the max8893a/max8893b/max8893c highly integrat - ed power-management ics integrate a high-efficiency 500ma step-down dc-dc converter, five low-dropout linear regulators, a load switch with ultra-low on-resis - tance, a usb high-speed switch, and a 400khz i 2 c serial interface. the step-down converter delivers over 500ma at i 2 c programmable output levels from 0.8v to 2.4v. it uses a proprietary hysteretic-pwm control scheme that switch - es up to 4mhz, allowing a trade-off between efficiency and tiny external components. the step-down converter also features dynamic voltage scaling (dvs) control. its output voltage ramps up with the i 2 c-controlled ramp rate from 1mv/ f s to 12mv/ f s. five low-dropout linear regulators feature low 45 f v rms output noise (ldo1, ldo4, and ldo5) and very low ground currents (ldo2 and ldo3). the usb high-speed switch is a high esd-protected dpdt analog switch. it is ideal for usb 2.0 hi-speed (480mbps) switching applications and also meets usb low- and full-speed requirements. the load switch fea - tures ultra-low on-resistance and operates from 0.8v to 2.4v input range. its rise time is i 2 c programmable to control the inrush current. the internal i 2 c interface provides flexible control on regulator on/off control, output voltage setting, step-down dynamic voltage scal - ing and ramp rate, and load switch timing . step-down dc-dc converter control scheme the max8893a/max8893b/max8893c step-down con - verter is optimized for high-efficiency voltage conver - sion over a wide load range, while maintaining excellent transient response, minimizing external component size, and output voltage ripple. the step-down converter also features an optimized on-resistance internal mosfet switch and synchronous rectifier to maximize efficiency. the ic utilizes a proprietary hysteretic-pwm control scheme that switches with nearly fixed frequency up to 4mhz allowing for ultra-small external components. its output current is guaranteed up to 500ma. when the step-down output voltage falls below the regu - lation threshold, the error comparator begins a switching cycle by turning on the high-side switch. this switch remains on until the minimum on-time (t on ) expires and the output voltage is in regulation or the current-limit threshold is exceeded. once off, the high-side switch remains off until the minimum off-time (t off ) expires and the output voltage again falls below the regulation threshold. during the off period, the low-side synchro - nous rectifier turns on and remains on until either the high-side switch turns on again or the inductor current reduces to the rectifier-off current threshold (i lxoff = 30ma (typ)). the internal synchronous rectifier elimi - nates the need for an external schottky diode. the step-down converter has the internal soft-start cir - cuitry with a fixed ramp to eliminate input current spikes when it is enabled. voltage positioning load regulation the step-down converter uses a unique feedback net - work. by taking feedback from the lx node, the usual phase lag due to the output capacitor is removed, mak - ing the loop exceedingly stable and allowing the use of very small ceramic output capacitors. this configuration causes the output voltage to shift by the inductor series resistance multiplied by the load current. this voltage- positioning load regulation greatly reduces overshoot during load transients, which effectively halves the peak-to-peak output-voltage excursions compared to traditional step-down converters . dynamic voltage scaling (dvs) control with ramp rate the step-down output voltage has a variable ramp rate that is set by the buckramp bits in the dvs ramp control register. this register controls the output- voltage ramp rate during a positive voltage change (for example, from 1.0v to 1.1v), and a negative voltage change (for example, from 1.1v to 1.0v). ramp rate adjustment range is from 1mv/ f s to 12mv/ f s in the step of 1mv/ f s . after the step-down converter is in regulation, its output voltage can dynamically ramp up at the rate set by the buckramp bits for a positive voltage change. for a negative voltage change, the decay rate of the output voltage depends on the size of the external load: a small load results in an output-voltage decay that is slower than the specified ramp rate and lx sinks current from the output capacitor to actively ramp down the output voltage; a large load (greater than cout x ramp rate) results in an output-voltage decay with the specified ramp rate. when the step-down converter is disabled, the output voltage decays to ground at a rate determined by the output capacitance, internal discharge resistance, and the external load. maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
29 low-dropout linear regulators the max8893a/max8893b/max8893c contain five low- dropout, low-quiescent-current, high-accuracy, linear regulators (ldos). the ldo output voltages are set through the i 2 c serial interface. the ldos include an internal reference, error amplifier, p-channel pass transistor, and internal programmable voltage-divider. each error amplifier compares the reference voltage to a feedback voltage and amplifies the difference. if the feedback voltage is lower than the reference voltage, the pass-transistor gate is pulled lower, allowing more current to pass to the output and increasing the output voltage. if the feedback voltage is too high, the pass- transistor gate is pulled up, allowing less current to pass to the output. default regulator output voltages the default regulator output voltages are set as shown in table 1. all regulator output voltages (buck, ldo1, ldo2, ldo3, ldo4, and ldo5) are programmable through the i 2 c serial interface. enable inputs (enbuck, enldo_, enls, enusb ) the max8893a/max8893b/max8893c have individ - ual enable inputs for each regulator, load switch, and usb switch. the individual enable inputs (enbuck, enldo1, enldo2, enldo3, enldo45, enls) are logically ored with the corresponding i 2 c serial inter - face control bit. enusb input is logically nanded with the eusb bit. see tables 2, 3, and 4 for enable logic truth tables. the enable inputs (enbuck, enldo_, and enls) are internally pulled to agnd by an 800k i (typ) pulldown resistor. enusb is internally pulled up to batt by an 800k (typ) pullup resistor. any valid enable input signal turns on the max8893a/ max8893b/max8893c. after the ic is up, the i 2 c inter - face is active and the ic can be reprogrammed through the i 2 c interface. to turn off the ic, both i 2 c bus and enable inputs must be low. all i 2 c register values return to the default value when no enable input signals are present. table 1. default regulator output voltages table 2. truth table for buck, ldo1 to ldo3, and load switch table 3. truth table for ldo4 and ldo5 part buck (v) ldo1 (v) ldo2 (v) ldo3 (v) ldo4 (v) ldo5 (v) max8893a 1.0 2.8 2.6 3.3 3.0 1.0 max8893b 1.0 2.6 2.6 3.3 3.3 2.8 max8893c 1.0 1.8 2.6 3.3 3.3 3.0 enable input (enbuck, enldo1, enldo2, enldo3, or enls) corresponding i 2 c on/off control bit corresponding regulator or switch 0 0 off 0 1 on 1 0 on 1 1 on enable input (enldo45) eldo4 bit eldo5 bit ldo4 ldo5 0 0 0 off off 0 0 1 o ff o n 0 1 0 o n o ff 0 1 1 on on 1 0 0 on on 1 1 1 on on maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
30 power-up sequencing drive enbuck or enldo_ high to turn on the buck converter or the corresponding ldos. when enbuck and enldo_ are connected together and driven from low to high, all the regulators are turned on with the preset power-up sequencing. there are time delays between each regulator to limit input current rush. the max8893a/max8893b/max8893c have different power-up time delays between each regulator. see the typ i cal operating characteristics for details. undervoltage lockout when v in rises above the undervoltage lockout thresh - old (2.85v typ), the max8893a/max8893b/max8893c can be enabled by driving any en_ high or enusb low. the uvlo threshold hysteresis is typically 0.5v. therefore, if v in falls below 2.35v (typ), the undervolt - age lockout circuitry disables all outputs and all internal registers are reset to default values . reference noise bypass (refbp) bypass refbp to agnd with a 0.1 f f ceramic capaci - tor to reduce noise on the ldo outputs. refbp is high impedance in shutdown. thermal-overload protection thermal-overload protection limits total power dissi - pation in the max8893a/max8893b/max8893c. the step-down converter and ldos have independent ther - mal protection circuits. when the junction temperature exceeds +160 n c, the ldo, or step-down thermal- overload protection circuitry disables the corresponding regulators, allowing the ic to cool. the ldo thermal- overload protection circuit enables the ldos after the ldo junction temperature cools down, resulting in pulsed ldo outputs during continuous thermal-overload conditions. the step-down converters thermal-overload protection circuitry enables the step-down converter after the junction temperature cools down. thermal- overload protection safeguards the ic in the event of fault conditions. usb high-speed switch the usb high-speed switch is a q 15kv esd-protected dpdt analog switch. it is ideal for usb 2.0 hi-speed (480mbps) switching applications and also meets usb low- and full-speed requirements. the usb switch is fully specified to operate from a single 2.7v to 5.5v supply. the switch is based on charge-pump- assisted n-channel architecture. the switch also features a shutdown mode to reduce the quiescent current. digital control input the usb high-speed switch provides a single-bit control logic input, cb. cb controls the position of the switches as shown in figure 7. driving cb rail-to-rail minimizes power consumption. table 4. truth table for usb switch figure 7. usb switch functional diagram/truth table enusb eusb bit usb switch 0 0 on 0 1 on 1 0 on 1 1 off cb batt no 1 nc 1 no 2 nc 2 com1 com2 0 enusb 0 1 0 cb 1 x off n0_ on off ? ? com_ hi-z on nc_ off off x = don't care. max8893a max8893b max8893c enusb maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
31 analog signal levels the on-resistance of the usb switch is very low and stable as the analog input signals are swept from ground to v in (see the typical operating characteristics ). these switches are bidirectional, allowing no_, nc_, and com_ to be configured as either inputs or outputs. the charge-pump-assisted n-channel architecture allows the switch to pass analog signals that exceed v in up to the overvoltage fault protection threshold. this allows usb signals that exceed v in to pass, allowing compliance with usb requirements for voltage levels. overvoltage fault protection the usb switch features overvoltage fault protection on com_. fault protection protects the switch and usb transceiver from damaging voltage levels. when volt - ages on com_ exceed the fault protection threshold (v fp ), com_, nc_, and no_ are high impedance. enable input ( enusb ) the usb switch features a shutdown mode that reduces the quiescent current supply and places com_ in high impedance. drive enusb high to place the usb switch in shutdown mode. drive enusb low to allow the usb switch to enter normal operation. load switch the max8893a/max8893b/max8893c include an ultra- low r on p-channel mosfet load switch. the switch has its own enable input, enls. when it is enabled, its output soft-starts with i 2 c programmed rising time to avoid inrush current. see table 8. the switch input is from the step-down converter output and can operate over the 0.8v to 2.4v range. with ls_aden bit set to 1, when the switch is disabled, an internal 100 resistor is connected between the load switch output and ground for quick discharging. i 2 c serial interface an i 2 c-compatible, 2-wire serial interface controls all the regulator output voltages, load switch timing, individual enable/disable control, and other parameters. the serial bus consists of a bidirectional serial-data line (sda) and a serial-clock input (scl). the max8893a/max8893b/ max8893c are slave-only devices, relying upon a master to generate a clock signal. the master initiates data transfer to and from the max8893a/max8893b/ max8893c and generates scl to synchronize the data transfer (figure 8). i 2 c is an open-drain bus. both sda and scl are bidi - rectional lines, connected to a positive supply voltage through a pullup resistor. they both have schmitt trig - gers and filter circuits to suppress noise spikes on the bus to assure proper device operation. figure 8. 2-wire serial interface timing detail scl sda t r t f t buf start condition stop condition repeated start condition start condition t su,sto t hd,sta t su,sta t hd,dat t su,dat t low t high t hd,sta maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
32 slave address a bus master initiates communication with a slave device (max8893a/max8893b/max8893c) by issuing a start condition followed by the slave address. the slave address byte consists of 7 address bits (0111110) and a read/write bit (rw). its address is 0x7c for write operations and 0x7d for read operations. after receiv - ing the proper address, the max8893a/max8893b/ max8893c issue an acknowledge by pulling sda low during the ninth clock cycle. bit transfer each data bit, from the most significant bit to the least significant bit, is transferred one by one during each clock cycle. during data transfer, the sda signal is allowed to change only during the low period of the scl clock and it must remain stable during the high period of the scl clock (figure 9). start and stop conditions both scl and sda remain high when the bus is not busy. the master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished com - municating with the max8893a/max8893b/max8893c, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (figure 10). both start and stop conditions are generated by the bus master. figure 9. bit transfer figure 10. start and stop conditions start condition (s) data line stable data valid data allowed to change stop condition (p) scl sda sda scl start condition stop condition maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
33 acknowledge the acknowledge bit is used by the recipient to hand - shake the receipt of each byte of data (figure 11). after data transfer, the master generates the acknowledge clock pulse and the recipient pulls down the sda line during this acknowledge clock pulse, such that the sda line stays low during the high duration of the clock pulse. when the master transmits the data to the max8893a/ max8893b/max8893c, it releases the sda line and the max8893a/max8893b/max8893c take the control of the sda line and generate the acknowledge bit. when sda remains high during this 9th clock pulse, this is defined as the not acknowledge signal. the master can then generate either a stop condition to abort the transfer, or a repeated start condition to start a new transfer. write operation the max8893a/max8893b/max8893c recognize the write-byte protocol as defined in the smbus? specifica - tion and shown in section a of figure 12. the write-byte protocol allows the i 2 c master device to send 1 byte of data to the slave device. the write-byte protocol requires a register pointer address for the subsequent write. the max8893a/max8893b/max8893c acknowledge any register pointer even though only a subset of those registers actually exists in the device. the write-byte protocol is as follows: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit (0x7c). 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave updates with the new data. 8) the slave acknowledges the data byte. 9) the master sends a stop condition. in addition to the write-byte protocol, the max8893a/ max8893b/max8893c can write to multiple registers as shown in section b of figure 12. this protocol allows the i 2 c master device to address the slave only once and then send data to a sequential block of registers starting at the specified register pointer. use the following procedure to write to a sequential block of registers: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit (0x7c). 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends the 8-bit register pointer of the first register to write. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave updates with the new data. 8) the slave acknowledges the data byte. 9) steps 6 to 8 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 10) the master sends a stop condition. figure 11. acknowledge smbus is a trademark of intel corp. sda by master sda by slave scl 1 2 8 9 acknowledge clock pulse for acknowledgement d7 d6 d0 start condition not acknowledge maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
34 read operation the method for reading a single register (byte) is shown in section a of figure 13. to read a single register: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a read bit (0x7d). 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address followed by a read bit. 8) the slave asserts an acknowledge by pulling sda low. 9) the slave sends the 8-bit data (contents of the register). 10) the master asserts an acknowledge by pulling sda low. 11) the master sends a stop condition. in addition, the max8893a/max8893b/max8893c can read a block of multiple sequential registers as shown in section b of figure 13. use the following procedure to read a sequential block of registers: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a read bit (0x7d). 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer of the first register in the block. 5) the slave acknowledges the register pointer. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address followed by a read bit. 8) the slave asserts an acknowledge by pulling sda low. 9) the slave sends the 8-bit data (contents of the register). 10) the master asserts an acknowledge by pulling sda low. 11) steps 9 and 10 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 12) the master sends a stop condition. figure 12. writing to the max8893a/max8893b/max8893c 1 s number of bits r/w slave address 7 0 18 register pointer 11 8 data 1 p 1 slave to master master to slave legend a. writing to a single register with the write byte protocol 1 s number of bits r/w slave address 7 0 18 register pointer x 1 a 18 data x 1 b. writing to multiple registers 8 data x+n-1 18 data x+n 1 number of bits p 8 data x+1 1 a a a a a a a a maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
35 figure 13. reading from the max8893a/max8893b/max8893c table 5. register map 1 s number of bits r/w slave address 7 0 18 register pointer 11 18 slave address 1 1 slave to master master to slave legend a. reading a single register 1 s number of bits r/w slave address 7 0 18 register pointer x 1 a 11 8 slave address 1 b. reading multiple registers 8 data x+1 1 8 data x+n-1 1 number of bits 8 data x 1 a a aa a a sr a 1 8 data 1 p 1 a a 1 1 sr ... 8 data x+n 11 a p r/w name table register address (hex) reset value type description on/off control table 6 0x00 0x01 r/w buck, ldo1Cldo5, load switch, and usb switch on/off control active discharge control table 7 0x01 0xff r/w active discharge enable/disable control for step-down converter and ldo regulators ls time control table 8 0x02 0x08 r/w load switch rising time, turn-on, and turn- off delay time control dvs ramp control table 9 0x03 0x09 r/w buck enable and ramp rate control buck table 10 0x04 0x02 r/w buck output voltage setting ldo1 table 11 0x05 0x0c 0x0a 0x02 r/w ldo1 output voltage setting ldo2 table 12 0x06 0x0e r/w ldo2 output voltage setting ldo3 table 13 0x07 0x11 r/w ldo3 output voltage setting ldo4 table 14 0x08 0x16 0x19 r/w ldo4 output voltage setting ldo5 table 15 0x09 0x02 0x14 0x16 r/w ldo5 output voltage setting sver table 16 0x46 n/a r only die type information maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
36 table 6. on/off control this register contains buck, ldo1?ldo5, usb switch, and load switch on/off controls. bit name description default value b7 (msb) ebuck 0 = buck is disabled 1 = buck is enabled 0 b6 els 0 = load switch is disabled 1 = load switch is enabled 0 b5 eldo1 0 = ldo1 is disabled 1 = ldo1 is enabled 0 b4 eldo2 0 = ldo2 is disabled 1 = ldo2 is enabled 0 b3 eldo3 0 = ldo3 is disabled 1 = ldo3 is enabled 0 b2 eldo4 0 = ldo4 is disabled 1 = ldo4 is enabled 0 b1 eldo5 0 = ldo5 is disabled 1 = ldo5 is enabled 0 b0 (lsb) eusb 0 = usb switch is enabled 1 = usb switch is disabled 1 register name on/off control register pointer 0x00 reset value 0x01 type read/write special features maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
37 table 7. active discharge control this register contains the active discharge enable bits for the buck, load switch, and ldo1?ldo5. register name active discharge control register pointer 0x01 reset value 0xff type read/write special features bit name description default value b7 (msb) buck_aden 0 = buck active discharge is disabled 1 = buck active discharge is enabled 1 b6 ls_aden 0 = load switch active discharge is disabled 1 = load switch active discharge is enabled 1 b5 ldo1 _aden 0 = ldo1 active discharge is disabled 1 = ldo1 active discharge is enabled 1 b4 ldo2 _aden 0 = ldo2 active discharge is disabled 1 = ldo2 active discharge is enabled 1 b3 ldo3 _aden 0 = ldo3 active discharge is disabled 1 = ldo3 active discharge is enabled 1 b2 ldo4 _aden 0 = ldo4 active discharge is disabled 1 = ldo4 active discharge is enabled 1 b1 ldo5 _aden 0 = ldo5 active discharge is disabled 1 = ldo5 active discharge is enabled 1 b0 (lsb) reserved for future use maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
38 table 8. ls time control this register contains the load switch timing controls. register name ls time control register pointer 0x02 reset value 0x08 type read/write special features bit name description default value b7 (msb) reserved for future use b6 reserved for future use b5 reserved for future use b4 lsrt load switch rising time control 00 = 10 f s 01 = 27 f s 10 = 100 f s 11 = 300 f s 01 b3 b2 lstod load switch turn-on delay time control 0 = load switch turn-on delay off 1 = load switch turn-on delay is 34 f s 0 b1 lstoffd load switch turn-off delay time control 00 = 11 f s 01 = 63 f s 10 = 177 f s 11 = 11 f s 00 b0 (lsb) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
39 table 9. dvs ramp control this register contains dvs enable/disable and ramp rate control for the step-down converter. register name dvs ramp control register pointer 0x03 reset value 0x09 type read/write special features bit name description default value b7 (msb) reserved for future use b6 reserved for future use b5 reserved for future use b4 endvs 0 = buck dvs is disabled 1 = buck dvs is enabled 0 b3 buckramp step-down output voltage ramp rate control 0000 (0x0) = 1mv/ f s 0001 (0x1) = 2mv/ f s 0010 (0x2) = 3mv/ f s 0011 (0x3) = 4mv/ f s 0100 (0x4) = 5mv/ f s 0101 (0x5) = 6mv/ f s 0110 (0x6) = 7mv/ f s 0111 (0x7) = 8mv/ f s 1000 (0x8) = 9mv/ f s 1001 (0x9) = 10mv/ f s 1010 (0xa) = 11mv/ f s 1011 (0xb) = 12 mv/ f s 1001 (0x9) b2 b1 b0 (lsb) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
40 table 10. buck this register contains the step-down converter output voltage controls. register name buck register pointer 0x04 reset value 0x02 type read/write special features bit name description default value b7 (msb) buck 00000000 (0x00) = 0.8v 00000001 (0x01) = 0.9v 00000010 (0x02) = 1.0v 00000011 (0x03) = 1.1v 00000100 (0x04) = 1.2v 00000101 (0x05) = 1.3v 00000110 (0x06) = 1.4v 00000111 (0x07) = 1.5v 00001000 (0x08) = 1.6v 00001001 (0x09) = 1.7v 00001010 (0x0a) = 1.8v 00001011 (0x0b) = 1.9v 00001100 (0x0c) = 2.0v 00001101 (0x0d) = 2.1v 00001110 (0x0e) = 2.2v 00001111 (0x0f) = 2.3v 00010000 (0x10) = 2.4v 00000010 (0x02) b6 b5 b4 b3 b2 b1 b0 (lsb) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
41 table 11. ldo1 this register contains ldo1 output voltage controls. register name on/off control register pointer 0x05 reset value 0x0c (max8893a) 0x0a (max8893b) 0x02 (max8893c) type read/write special features bit name description default value b7 (msb) ldo1 00000000 (0x00) = 1.6v 00000001 (0x01) = 1.7v 00000010 (0x02) = 1.8v 00000011 (0x03) = 1.9v 00000100 (0x04) = 2.0v 00000101 (0x05) = 2.1v 00000110 (0x06) = 2.2v 00000111 (0x07) = 2.3v 00001000 (0x08) = 2.4v 00001001 (0x09) = 2.5v 00001010 (0x0a) = 2.6v 00001011 (0x0b) = 2.7v 00001100 (0x0c) = 2.8v 00001101 (0x0d) = 2.9v 00001110 (0x0e) = 3.0v 00001111 (0x0f) = 3.1v 00010000 (0x10) = 3.2v 00010001 (0x11) = 3.3v max8893a 00001100 (0x0c) max8893b 00001010 (0x0a) max8893c 00000010 (0x02) b6 b5 b4 b3 b2 b1 b0 (lsb) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
42 table 12. ldo2 this register contains ldo2 output voltage controls. register name ldo2 register pointer 0x06 reset value 0x0e type read/write special features bit name description default value b7 (msb) ldo2 00000000 (0x00) = 1.2v 00000001 (0x01) = 1.3v 00000010 (0x02) = 1.4v 00000011 (0x03) = 1.5v 00000100 (0x04) = 1.6v 00000101 (0x05) = 1.7v 00000110 (0x06) = 1.8v 00000111 (0x07) = 1.9v 00001000 (0x08) = 2.0v 00001001 (0x09) = 2.1v 00001010 (0x0a) = 2.2v 00001011 (0x0b) = 2.3v 00001100 (0x0c) = 2.4v 00001101 (0x0d) = 2.5v 00001110 (0x0e) = 2.6v 00001111 (0x0f) = 2.7v 00010000 (0x10) = 2.8v 00010001 (0x11) = 2.9v 00010010 (0x12) = 3.0v 00010011 (0x13) = 3.1v 00010100 (0x14) = 3.2v 00010101 (0x15) = 3.3v 00001110 (0x0e) b6 b5 b4 b3 b2 b1 b0 (lsb) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
43 table 13. ldo3 this register contains ldo3 output voltage controls. register name ldo3 register pointer 0x07 reset value 0x11 type read/write special features bit name description default value b7 (msb) ldo3 00000000 (0x00) = 1.6v 00000001 (0x01) = 1.7v 00000010 (0x02) = 1.8v 00000011 (0x03) = 1.9v 00000100 (0x04) = 2.0v 00000101 (0x05) = 2.1v 00000110 (0x06) = 2.2v 00000111 (0x07) = 2.3v 00001000 (0x08) = 2.4v 00001001 (0x09) = 2.5v 00001010 (0x0a) = 2.6v 00001011 (0x0b) = 2.7v 00001100 (0x0c) = 2.8v 00001101 (0x0d) = 2.9v 00001110 (0x0e) = 3.0v 00001111 (0x0f) = 3.1v 00010000 (0x10) = 3.2v 00010001 (0x11) = 3.3v 00010001 (0x11) b6 b5 b4 b3 b2 b1 b0 (lsb) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
44 table 14. ldo4 this register contains ldo4 output voltage controls. register name ldo4 register pointer 0x08 reset value 0x16(max8893a) 0x19(max8893b/max8893c) type read/write special features bit name description default value b7 (msb) ldo4 00000000 (0x00) = 0.8v 00000001 (0x01) = 0.9v 00000010 (0x02) = 1.0v 00000011 (0x03) = 1.1v 00000100 (0x04) = 1.2v 00000101 (0x05) = 1.3v 00000110 (0x06) = 1.4v 00000111 (0x07) = 1.5v 00001000 (0x08) = 1.6v 00001001 (0x09) = 1.7v 00001010 (0x0a) = 1.8v 00001011 (0x0b) = 1.9v 00001100 (0x0c) = 2.0v 00001101 (0x0d) = 2.1v 00001110 (0x0e) = 2.2v 00001111 (0x0f) = 2.3v 00010000 (0x10) = 2.4v 00010001 (0x11) = 2.5v 00010010 (0x12) = 2.6v 00010011 (0x13) = 2.7v 00010100 (0x14) = 2.8v 00010101 (0x15) = 2.9v 00010110 (0x16) = 3.0v 00010111 (0x17) = 3.1v 00011000 (0x18) = 3.2v 00011001 (0x19) = 3.3v max8893a 00010110 (0x16) max8893b /max8893c 00011001 (0x19) b6 b5 b4 b3 b2 b1 b0 (lsb) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
45 table 15. ldo5 this register contains ldo5 output voltage controls. register name ldo5 register pointer 0x09 reset value 0x02 (max8893a) 0x14 (max8893b) 0x16 (max8893c) type read/write special features bit name description default value b7 (msb) ldo5 00000000 (0x00) = 0.8v 00000001 (0x01) = 0.9v 00000010 (0x02) = 1.0v 00000011 (0x03) = 1.1v 00000100 (0x04) = 1.2v 00000101 (0x05) = 1.3v 00000110 (0x06) = 1.4v 00000111 (0x07) = 1.5v 00001000 (0x08) = 1.6v 00001001 (0x09) = 1.7v 00001010 (0x0a) = 1.8v 00001011 (0x0b) = 1.9v 00001100 (0x0c) = 2.0v 00001101 (0x0d) = 2.1v 00001110 (0x0e) = 2.2v 00001111 (0x0f) = 2.3v 00010000 (0x10) = 2.4v 00010001 (0x11) = 2.5v 00010010 (0x12) = 2.6v 00010011 (0x13) = 2.7v 00010100 (0x14) = 2.8v 00010101 (0x15) = 2.9v 00010110 (0x16) = 3.0v 00010111 (0x17) = 3.1v 00011000 (0x18) = 3.2v 00011001 (0x19) = 3.3v max8893a 00000010 (0x02) max8893b 00010100 (0x14) max8893c 00010110 (0x16) b6 b5 b4 b3 b2 b1 b0 (lsb) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
46 applications information step-down converter input capacitor the input capacitor, c in1 , reduces the current peaks drawn from the battery or input power source and reduc - es switching noise in the ic. the impedance of c in1 at the switching frequency should be kept very low. ceramic capacitors with x5r or x7r temperature characteristics are highly recommended due to their small size, low esr, and small temperature coefficients. due to the step-down converters fast soft-start, the input capacitance can be very low. for most applications, a 2.2 f f capacitor is suf - ficient. connect c in1 as close as possible to the ic to minimize the impact of pcb trace inductance. for other input capacitors, use a 2.2 f f ceramic capaci - tor from in2 to ground and a 2.2 f f ceramic capacitor from batt to ground. output capacitor the output capacitor, c buck , is required to keep the output voltage ripple small and to ensure regulation loop stability. c buck must have low impedance at the switch - ing frequency. ceramic capacitors with x5r or x7r temperature characteristics are highly recommended due to their small size, low esr, and small temperature coefficients. due to the unique feedback network, the output capacitance can be very low. for most applica - tions a 2.2 f f capacitor is sufficient. for optimum load- transient performance and very low output ripple, the output capacitor value in f f should be equal to or larger than the inductor value in f h. inductor selection the recommended inductor for the step-down converter is from 1.0 f h and 4.7 f h. low inductance values are physically smaller, but require faster switching, resulting in some efficiency loss. the inductors dc current rating needs to be only 100ma greater than the applications maximum load current because the step-down converter features zero current overshoot during startup and load transients. for output voltages above 2.0v, when light load efficien - cy is important, the minimum recommended inductor is 2.2 f h. for optimum voltage-positioning load transients, choose an inductor with dc series resistance in the 50m to 150m range. to achieve higher efficiency at heavy loads (above 200ma) or minimum load regulation (but some transient overshoot), the inductor resistance should be kept below 100m. for light -oad applications up to 200ma, much higher resistance is acceptable with very little impact on performance. see table 17 for some suggested inductors. table 16. sver this register contains the max8893a/max8893b/max8893c version number. register name sver register pointer 0x46 reset value n/a type read special features bit name description default value b7 (msb) reserved for future use b6 reserved for future use b5 reserved for future use b4 reserved for future use b3 reserved for future use b2 reserved for future use b1 sver 00 = max8893a 01 = max8893b 10 = max8893c b0 (lsb) maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
47 table 17. suggested inductors manufacturer series inductance ( f h) esr (m i ) isat (ma) dimensions (l typ o w typ o h max ) (mm) taiyo yuden lb2012 1.0 2.2 150 230 300 240 2.0 x 1.25 x 1.45 lb2016 1.0 1.5 2.2 3.3 90 110 130 200 455 350 315 280 2.0 x 1.6 x 1.8 lb2518 1.0 1.5 2.2 3.3 60 70 90 110 500 400 340 270 2.5 x 1.8 x 2.0 lbc2518 1.0 1.5 2.2 3.3 4.7 80 110 130 160 200 775 660 600 500 430 2.5 x 1.8 x 2.0 murata lqh32c_53 1.0 2.2 4.7 60 100 150 1000 790 650 3.2 x 2.5 x 1.7 lqm43fn 2.2 4.7 100 170 400 300 4.5 x 3.2 x 0.9 toko d310f 1.5 2.2 3.3 130 170 190 1230 1080 1010 3.6 x 3.6 x 1.0 d312c 1.5 2.2 2.7 3.3 100 120 150 170 1290 1140 980 900 3.6 x 3.6 x 1.2 sumida cdrh2d11 1.5 2.2 3.3 4.7 50 80 100 140 900 780 600 500 3.2 x 3.2 x 1.2 maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
48 capacitors for ldos for ldos, the required output capacitance is depen - dent on the load currents. with rated maximum load currents, 2.2 f f (typ) capacitors are recommended for ldo1, ldo2, ldo3, and ldo5 and a 1.0 f f capacitor is recommended for ldo4. for loads less than 150ma, it is sufficient to use 1.0 f f capacitors for stable operation over the full temperature range for ldo1, ldo2, ldo3, and ldo5. reduce output noise and improve load tran - sient response, stability, and power-supply rejection by using larger output capacitors. usb high-speed switch usb switching the usb high-speed switch is fully compliant with the usb 2.0 specification. the low on-resistance and low on-capacitance of these switches make it ideal for high- performance switching applications. it is ideal for routing usb data lines (see figure 14) and for applications that require switching between multiple usb hosts (see figure 15). the usb switch also features overvoltage fault pro - tection to guard systems against shorts to the usb vbus voltage that is required for all usb applications. extended esd protection as with all maxim devices, esd-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. com1 and com2 are further protected against static electricity. the state-of-the-art structures are developed to protect these pins against esd up to 15kv without damage. the esd structures withstand high esd in nor - mal operation and when the device is powered down. after an esd event, the usb switch continues to function without latchup. the usb high-speed switch is characterized for protec - tion to the following limits: u 15kv using human body model u 8kv using iec 61000-4-2 contact discharge method u 15kv using iec 61000-4-2 air-gap discharge method figure 14. usb data routing/typical application circuit figure 15. switching between multiple usb hosts v bus asic i asic ii hi-speed usb transceiver hi-speed usb transceiver d+ d- d+ nc1 no1 nc2 no2 d- d+ d- gnd usb connector com1 com2 max8893a max8893b max8893c nc1 no1 d+ d+ d- d+ d- d- nc2 no2 com1 com2 hi-speed usb transceiver usb host i max8893a max8893b max8893c usb host ii maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
49 pcb layout and routing high switching frequencies and relatively large peak currents make the pcb layout a very important aspect of design. good design minimizes excessive emi on the voltage gradients in the ground plane that can result in instability or regulation errors. connect the input and out - put capacitors as close as possible to the ic. connect the inductor as close as possible to the ic and keep the traces short, direct, and wide. connect agnd to the exposed pad directly under the ic. connect agnd and pgnd to the ground plane. keep noisy traces, such as the lx node, as short as possible. usb hi-speed requires careful pcb layout with 45 controlled-impedance matched traces of equal lengths. ensure that bypass capacitors are as close as possible to the ic. use large ground planes where possible. refer to the max8893 evaluation kit for an example pcb layout design. typical operating circuit in1 input 2.7v to 5.5v 2.2f v ls v buck 0.8v to 2.4v v ldo1 1.6v to 3.3v v ldo2 1.2v to 3.3v v ldo3 1.6v to 3.3v v ldo4 0.8v to 3.3v v ldo5 0.8v to 3.3v 1.0f 2.2f 2.2h 2.2f 2.2f 2.2f 1f 2.2f 0.1f 2.2f 2.2f i 2 c ls on/off buck on/off ldo1 on/off ldo2 on/off ldo3 on/off ldo4/ldo5 on/off usb on/off usbsel buck ls agnd batt com2 com1 cb enusb enldo45 enldo3 enldo2 enldo1 enbuck enls refbp in2 ldo1 ldo2 ldo3 ldo4 ldo5 nc1 nc2 no2 no1 pgnd lx sda scl max8893a max8893b max8893c maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
50 chip information process: bicmos package type package code document no. 30 wlp w302a3+2 21-0016 package information for the latest package outline information and land patterns, go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a dif - ferent suffix character, but the drawing pertains to the package regardless of rohs status. maxim integrated pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 51 ? 2010 maxim integrated maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/09 initial release 1 2/10 added new tocs 53, 54, and 55 to typical operating characteristics section 21 pmics for multimedia application processors in a 3.0mm x 2.5mm wlp max8893a/max8893b/max8893c

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